.PHONY: build writefpga clean

SRC_SV=./src/signal_proc_with_adc_dac_top.sv ./src/SPI_MASTER.sv ./src/spi_adc_sampling.sv ./src/spi_dac_output.sv ./src/signal_processing.sv ./src/freq_filter.sv ./src/freq_filter_coef_rom.sv
SRC_IP=./src/ipcore/fft/fft.v ./src/ipcore/ifft/ifft.v ./src/ipcore/fifo_real/fifo_real.v ./src/ipcore/fifo_complex/fifo_complex.v
SRC_CST=./src/signal_proc_with_adc_dac.cst
SRC_SDC=./src/signal_proc_with_adc_dac.sdc
GW_PROJ_TCL=project.tcl
OUT_FS=./impl/pnr/signal_proc_with_adc_dac.fs

build: $(OUT_FS)
$(OUT_FS) : $(GW_PROJ_TCL) $(SRC_SV) $(SRC_IP) $(SRC_CST) $(SRC_SDC)
	gw_sh $(GW_PROJ_TCL)

$(SRC_IP):
	$(error Error! IP source code has not been generated. Please generate these first following README.md)

writefpga: $(OUT_FS)
	openFPGALoader $(OUT_FS)

clean:
	$(RM) signal_proc_with_adc_dac.gprj
	$(RM) signal_proc_with_adc_dac.gprj.user
	$(RM) -r impl
