コンピューター・サイエンス＆テクノロジ専門誌

wire count_enable;
logic [3:0] counter_reg[2];
logic [3:0] counter_next_value[2];
logic [1:0] carry;

// 1桁目の実装
// 加算回路
always_comb begin
if (carry[0] == 1'b1) begin
if (counter_reg[0] == 4'd9) begin
counter_next_value[0] = 4'd0;
carry[1] = 1'b1;
end else begin
counter_next_value[0] = counter_reg[0] + 4'd1;
carry[1] = 1'b0;
end
end else begin
counter_next_value[0] = counter_reg[0];
carry[1] = 1'b0;
end
end
// レジスタ
always_ff @ (posedge clk) begin
counter_reg[0] <= counter_next_value[0];
end

// 2桁目の実装
// 加算回路
always_comb begin
if (carry[1] == 1'b1) begin
if (counter_reg[1] == 4'd9) begin
counter_next_value[1] = 4'd0;
carry[2] = 1'b1;
end else begin
counter_next_value[1] = counter_reg[1] + 4'd1;
carry[2] = 1'b0;
end
end else begin
counter_next_value[1] = counter_reg[1];
carry[2] = 1'b0;
end
end
// レジスタ
always_ff @ (posedge clk) begin
counter_reg[1] <= counter_next_value[1];
end